1. Field of the Invention
The present invention relates generally to decoders, and more particularly to decoders which are achieved using bifet technology.
2. Related Art
A decoder is a device having input and output lines. The decoder selects one of its output lines according to the combination of values present on its input lines. When selecting an output line, the decoder sets the output line to either a low voltage value or a high voltage value, depending on whether the output lines are high or low, respectively, when not selected by the decoder. As used herein, the terms "select" and "enable" are used interchangeably.
Decoders are often used as access controllers for memory devices. This is shown in FIG. 1, where a decoder 104 controls access to a memory device 108.
The decoder 104 has N input lines 102 and 2.sup.N output lines 106 (the output lines 106 are also called word/bit lines 106 when the decoder 104 is used as an access controller as shown in FIG. 1). The memory device 108 has 2.sup.N rows and W memory cells per row. A one-to-one correspondence exists between the 2.sup.N word/bit lines 106 and the 2.sup.N rows of the memory device 108.
Ordinarily, the decoder 104 maintains the word/bit lines 106 in an unenabled state. When it is desired to read from or write to a row 114 of the memory device 108, an address of the row 114 is placed on the input lines 102. In response to the address, the decoder 104 enables a word/bit line 116 which corresponds to the row 114. The decoder 104 maintains the other word/bit lines in the unenabled state. Once the word/bit line 116 is enabled, it is possible to either read from or write to the memory cells associated with the row 114 by means of data lines 110. A selection line 112 may be provided to select specific memory cells in the row 114 for reading and writing.
A conventional decoder 104' is shown in FIG. 2. The conventional decoder 104' contains first decoders 212, 214 and second decoders 202.
The first decoders 212, 214 each contain four input lines 216, 218 (which correspond to the input lines 102 in F1G. 1) and sixteen output lines 226, 228.
While only one second decoder 202 is shown in F1G. 2, in practice the conventional decoder 104' contains 256 second decoders 202. The second decoders 202 contain word/bit lines 224, which correspond to the word/bit lines 106 in F1G. 1.
The second decoder 202 contains only metal oxide semiconductor field effect transistors (MOSFET), and specifically negative field effect transistors (NFET) 208, 210 and positive field effect transistors (PFET) 204, 206. Circuits using metal oxide semiconductor NFETs and PFETs are often called complementary metal oxide semiconductors (CMOS).
The second decoder 202 has two input nodes 230, 232. The output lines 226, 228 are connected to the input nodes 230, 232, which are in turn connected to the gates of the NFETs 208, 210 and the PFETs 204, 206. Each of the second decoders 202 is connected to and receives input from a different combination of the output lines 226, 228.
In operation, an 8 bit address is divided into two 4 bit addresses. The two 4 bit addresses are applied to the first decoders 212, 214 on the input lines 216, 218. Normally, the first decoders 212, 214 maintain the output lines 226, 228 at a high voltage state, such that the output lines 226, 228 are not enabled. In response to the 4 bit addresses, the first decoders 212, 214 each cause one of their respective output lines 226, 228 to go to a low voltage state, such that the output lines 226, 228 in the low voltage state are enabled.
For any particular second decoder 202, if either or both of its input nodes 230, 232 (which are connected to the output lines 226, 228) are in a high voltage state, then either or both NFETs 208, 210 are conductive, and at least one of the PFETs 204, 206 is nonconductive. As a result, the word/bit line 224 is pulled down to a low voltage state, such that the word/bit line 224 is not enabled.
If the input nodes 230, 232 are both at a low voltage state, then the NFETs 208, 210 are nonconductive and the PFETs 204, 206 are conductive. As a result, the word/bit line 224 is pulled up to a high voltage state, such that the word/bit line 224 is enabled.
While representing a functional decoder 104, the conventional decoder 104' is flawed with respect to performance and density. Specifically, the conventional decoder 104' is relatively slow in operation because it uses only field effect transistors (FET) 204, 206, 208, 210. In general, FETs are relatively slower than other transistor types (such as bipolar). Also, the density of the conventional decoder 104' is relatively low because for a given driving power, FETs are physically larger than other transistor types (such as bipolar).
Another conventional decoder 104" is shown in F1G. 3. The conventional decoder 104" contains the first decoders 212, 214. The structure and operation 15 of the first decoders 212, 214 are as described above with reference to F1G. 2.
The conventional decoder 104" also contains second decoders 322. While only one second decoder 322 is shown in F1G. 3, in practice the conventional decoder 104" contains 256 second decoders 322. The second decoders 322 contain word/bit lines 314, which correspond to the word/bit lines 106 in FIG. 1.
The second decoder 322 contains only bipolar transistors 304, 306, 308. The second decoder 322 has two input nodes 324, 326. The output lines 226, 228 are connected to the input nodes 324, 326, which are in turn connected to the bases of the bipolar transistors 306, 308. Each of the second decoders 322 is connected to and receives input from a different combination of the output lines 226, 228.
In operation, an 8 bit address is divided into two 4 bit addresses. The two 4 bit addresses are applied to the first decoders 212, 214 on the input lines 216, 218. Normally, the first decoders 212, 214 maintain the output lines 226, 228 at a high voltage state, such that the output lines 226, 228 are not enabled. In response to the 4 bit addresses, the first decoders 212, 214 each cause one of their respective output lines 226, 228 to go to a low voltage state, such that the output lines 226, 228 in the low voltage state are enabled.
The bipolar transistors 306, 308 represent a NOR gate. The bipolar transistor 304 represents an emitter follower.
For any particular second decoder 322, if either or both of its input nodes 324, 326 are at a high voltage state, then at least one of the bipolar transistors 306, 308 is conductive. Consequently, the base of the bipolar transistor 304 is held at a low voltage state. As a result, the word/bit line 314 is pulled down to a low voltage state, such that the word/bit line 314 is not enabled.
If the input nodes 306, 308 are both at a low voltage state, then the bipolar transistors 306, 308 are nonconductive. Consequently, the base of the bipolar transistor 304 is pulled up to a high voltage state. As a result, the word/bit line 314 is pulled up to a high voltage state, such that the word/bit line 314 is enabled.
The conventional decoder 104" represents a functional decoder 104. Also, because it uses only bipolar transistors 304, 306, 308, the conventional decoder 104" solves the performance and density problems of the conventional decoder 104' since bipolar transistors are generally faster and physically smaller than FETs.
However, the conventional decoder 104" is flawed with respect to power dissipation. As shown in FIG. 3, the second decoders 322 always draw a significant amount of current. For example, while in the unenable state, the second decoders 322 draw current (and dissipate power) through the bipolar transistors 306, 308. While in the enabled state, the second decoders 322 draw current (and dissipate power) through the bipolar transistor 304.
FIG. 10 shows a conventional driving circuit of a decoder. Input to a decoder driving circuit would be the output of a decoding circuit of a decoder. For example, input line 1002 could be connected to the collectors of bipolar transistors 306 and 308 of F1G. 3. The driving circuit uses NPN transistor 1004 in an emitter-follower configuration.
The circuit is connected as follows. The emitter-collector path of NPN transistor 1004 is connected between an output line 1006 and V.sub.CC 1008. The base 1009 of the NPN transistor 1004 is connected to input line 1002. A resistor 1010 is connected between the emitter 1011 and V.sub.EE 1012. Output line 1006 is also connected to emitter 1011.
The circuit operates as follows. A low voltage on input line 1002 renders NPN transistor 1004 nonconductive. The level of output line 1006 would then be the level of V.sub.EE 1012. A high voltage on input line 1002 renders the transistor conductive. The voltage at emitter 1011 would be 1 V.sub.BE below the base voltage. Thus, even with an uplevel input of V.sub.CC, the uplevel output of the circuit could be no more than 1 V.sub.BE below V.sub.CC.
The emitter-follower configuration could be used to construct a fast, low density decoder with the ability to drive a large load. However, when used to drive a word line in a memory array, the relatively low maximum uplevel output of such a circuit would limit both the speed at which cells could be read and the degree of reliability with which cells could be written.
FIG. 11 shows a second conventional driving circuit of a decoder. The circuit uses a PNP transistor 1102 in a collector-follower configuration and a Shotkey diode 1104 to allow for a high uplevel output without saturating the transistor.
The circuit is connected as follows. The emitter-collector path of PNP transistor 1102 is connected between high voltage supply V.sub.CC 1106 and output line 1108. The anode-cathode path of Shotkey diode 1104 is connected between the collector 1109 and base 1111 of PNP transistor 1102. A resistor 1110 is connected between collector 1109 and low voltage supply V.sub.EE 1112. Input line 1114 is connected to base 1111. Output line 1108 is connected to collector 1109.
The circuit operates as follows. A high voltage on input line 1114 renders PNP transistor 1102 nonconductive. Voltage level on output line 1108 would then equal V.sub.EE 1112.
A low voltage on input line 1114 renders PNP transistor 1102 conductive. This enables V.sub.CC 1106 to pull up the voltage levels at collector 1109 and Shotkey diode 1104. Shotkey diode 1104 then pulls up the voltage level of base 1111. As the voltage at base rises, PNP transistor 1102 becomes less conductive, thus lowering the collector 1109 and base 1111 voltages.
To obtain maximum uplevel output, the size of Shotkey diode 1104 is such that the base voltage stabilizes just less than 1 V.sub.BE below V.sub.CC 1106. This voltage is the highest level at which PNP transistor 1102 will be conductive. The size of Shotkey diode 1104 is also such that collector 1109 stabilizes at a higher level than that of base 1111. Shotkey diode 1104 enables this to be accomplished without saturating (and therefore increasing switching time of) PNP transistor 1102.
A PNP transistor in a collector-follower configuration with a Shotkey diode could be used to construct a high performance decoder which produces a high uplevel voltage and dissipates little power. However, because Shotkey diodes are surface-interface rather than diffuse, this circuit presents potential yield problems in chip fabrication. Also, this circuit would require using a stand-alone Shotkey diode and would thus substantially increase the size of the decoder.
Therefore, there is a need for a high performance, high density decoder which produces a high uplevel voltage and dissipates little power and which does not use a Shotkey diode.